In the semiconductor industry, there is a trend to fabricate higher device densities. To achieve higher and higher densities per chip, efforts continue to scale down device dimensions (e.g., at submicron levels) on semiconductor wafers. For example, smaller and smaller feature sizes are being fabricated on integrated circuits (ICs) within small rectangular portions of the wafer, commonly known as dies. Examples of such features include width and spacing of interconnecting lines, spacing and diameter of contact holes and surface geometry such as corners and edges. In order to scale down device dimensions, precision control of the fabrication process is required. The dimension of and between features typically is referred to as critical dimensions or CD. Reducing CDs and reproducing more accurate CDs facilitates achieving higher device densities through scaled down dimensions and increased packing.
The process of manufacturing semiconductors or ICs typically includes numerous steps (e.g., exposing, baking, developing, etc.), during which hundreds of copies of an integrated circuit can be formed on a single wafer, and more particularly on each die of the wafer. In many of these steps, material is overlayed or removed from existing layers at specific locations to form desired elements of the integrated circuit. Generally, the manufacturing process involves creating several patterned layers on and into a substrate that ultimately forms the complete integrated circuit. This layering process creates electrically active regions in and on the semiconductor wafer surface. A
The design of complex semiconductors or ICs can be a difficult task and errors in design can result in silicon failure or re-masking during fabrication. Many of these errors can be spotted in the semiconductor or IC design before the design is taped-out or released to fabrication. Bad design practices resulting in errors can produce a bad silicon chip in fabrication even when the errors can be identified prior to fabrication. However, manually checking the design is a time consuming task even when the errors are easily noticed. For example, a flash memory design can have several million transistors that will need to be reviewed. In the case of modern central processing units (CPUs), the transistor count can be as high as several hundreds of millions transistors. Accordingly, the difficult task of manual review could result in errors going unnoticed during design.